SoC Root Canal!

Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs

Authors

  • Pantea Kiaei Worcester Polytechnic Institute, Worcester, MA 01609, USA
  • Patrick Schaumont Worcester Polytechnic Institute, Worcester, MA 01609, USA

DOI:

https://doi.org/10.46586/tches.v2022.i4.751-773

Keywords:

side-channel analysis, design-time methodology, micro-architecture, root-cause analysis

Abstract

Finding the root cause of power-based side-channel leakage becomes harder when multiple layers of design abstraction are involved. While side-channel leakage originates in processor hardware, the dangerous consequences may only become apparent in the cryptographic software that runs on the processor. This contribution presents RootCanal, a methodology to explain the origin of side-channel leakage in a software program in terms of the underlying micro-architecture and system architecture. We simulate the hardware power consumption at the gate level and perform a non-specific test to identify the logic gates that contribute most sidechannel leakage. Then, we back-annotate those findings to the related activities in the software. The resulting analysis can automatically point out non-trivial causes of side-channel leakages. To illustrate RootCanal’s capabilities, we discuss a collection of case studies.

Downloads

Published

2022-08-31

How to Cite

Kiaei, P., & Schaumont, P. (2022). SoC Root Canal! Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022(4), 751–773. https://doi.org/10.46586/tches.v2022.i4.751-773

Issue

Section

Articles