When Bad News Become Good News

Towards Usable Instances of Learning with Physical Errors

Authors

  • Davide Bellizia UCLouvain, ICTEAM, Crypto Group, Louvain-la-Neuve, Belgium
  • Clément Hoffmann UCLouvain, ICTEAM, Crypto Group, Louvain-la-Neuve, Belgium
  • Dina Kamel UCLouvain, ICTEAM, Crypto Group, Louvain-la-Neuve, Belgium
  • Pierrick Méaux Luxembourg University, SnT, Luxembourg
  • François-Xavier Standaert UCLouvain, ICTEAM, Crypto Group, Louvain-la-Neuve, Belgium

DOI:

https://doi.org/10.46586/tches.v2022.i4.1-24

Keywords:

Learning With Errors, Physical Assumptions, FPGA Implementations

Abstract

Hard physical learning problems have been introduced as an alternative option to implement cryptosystems based on hard learning problems. Their high-level idea is to use inexact computing to generate erroneous computations directly, rather than to first compute correctly and add errors afterwards. Previous works focused on the applicability of this idea to the Learning Parity with Noise (LPN) problem as a first step, and formalized it as Learning Parity with Physical Noise (LPPN). In this work, we generalize it to the Learning With Errors (LWE) problem, formalized as Learning With Physical Errors (LWPE). We first show that the direct application of the design ideas used for LPPN prototypes leads to a new source of (mathematical) data dependencies in the error distributions that can reduce the security of the underlying problem. We then show that design tweaks can be used to avoid this issue, making LWPE samples natively robust against such data dependencies. We additionally put forward that these ideas open a quite wide design space that could make hard physical learning problems relevant in various applications. And we conclude by presenting a first prototype FPGA design confirming our claims.

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Published

2022-08-31

How to Cite

Bellizia, D., Hoffmann, C., Kamel, D., Méaux, P., & Standaert, F.-X. (2022). When Bad News Become Good News: Towards Usable Instances of Learning with Physical Errors. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022(4), 1–24. https://doi.org/10.46586/tches.v2022.i4.1-24

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Articles