A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium

Authors

  • Cankun Zhao School of Integrated Circuits, Tsinghua University, Beijing, China
  • Neng Zhang School of Integrated Circuits, Tsinghua University, Beijing, China
  • Hanning Wang School of Integrated Circuits, Tsinghua University, Beijing, China
  • Bohan Yang School of Integrated Circuits, Tsinghua University, Beijing, China
  • Wenping Zhu School of Integrated Circuits, Tsinghua University, Beijing, China
  • Zhengdong Li School of Integrated Circuits, Tsinghua University, Beijing, China
  • Min Zhu Wuxi Micro Innovation Integrated Circuit Design Co., Ltd., Wuxi, China
  • Shouyi Yin School of Integrated Circuits, Tsinghua University, Beijing, China
  • Shaojun Wei School of Integrated Circuits, Tsinghua University, Beijing, China
  • Leibo Liu School of Integrated Circuits, Tsinghua University, Beijing, China

DOI:

https://doi.org/10.46586/tches.v2022.i1.270-295

Keywords:

CRYSTALS-Dilithium, FPGA, post-quantum cryptography, digital signature, module learning with errors

Abstract

The lattice-based CRYSTALS-Dilithium scheme is one of the three thirdround digital signature finalists in the National Institute of Standards and Technology Post-Quantum Cryptography Standardization Process. Due to the complex calculations and highly individualized functions in Dilithium, its hardware implementations face the problems of large area requirements and low efficiency. This paper proposes several optimization methods to achieve a compact and high-performance hardware architecture for round 3 Dilithium. Specifically, a segmented pipelined processing method is proposed to reduce both the storage requirements and the processing time. Moreover, several optimized modules are designed to improve the efficiency of the proposed architecture, including a pipelined number theoretic transform module, a SampleInBall module, a Decompose module, and three modular reduction modules. Compared with state-of-the-art designs for Dilithium on similar platforms, our implementation requires 1.4×/1.4×/3.0×/4.5× fewer LUTs/FFs/BRAMs/DSPs, respectively, and 4.4×/1.7×/1.4× less time for key generation, signature generation, and signature verification, respectively, for NIST security level 5.

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Published

2021-11-19

How to Cite

Zhao, C., Zhang, N., Wang, H., Yang, B., Zhu, W., Li, Z., Zhu, M., Yin, S., Wei, S., & Liu, L. (2021). A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022(1), 270–295. https://doi.org/10.46586/tches.v2022.i1.270-295

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Section

Articles