Improved Leakage-Resistant Authenticated Encryption based on Hardware AES Coprocessors
Keywords:Leakage-Resilient Cryptography, Authenticated Encryption, Secure Software Updates, Ciphertext Integrity, ARM Cortex, Differental Power Analysis
We revisit Unterstein et al.’s leakage-resilient authenticated encryption scheme from CHES 2020. Its main goal is to enable secure software updates by leveraging unprotected (e.g., AES, SHA256) coprocessors available on low-end microcontrollers. We show that the design of this scheme ignores an important attack vector that can significantly reduce its security claims, and that the evaluation of its leakage-resilient PRF is quite sensitive to minor variations of its measurements, which can easily lead to security overstatements. We then describe and analyze a new mode of operation for which we propose more conservative security parameters and show that it competes with the CHES 2020 one in terms of performances. As an additional bonus, our solution relies only on AES-128 coprocessors, an
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Copyright (c) 2021 Olivier Bronchain, Charles Momin, Thomas Peters, François-Xavier Standaert
This work is licensed under a Creative Commons Attribution 4.0 International License.