Attacking and Defending Masked Polynomial Comparison for Lattice-Based Cryptography

Authors

  • Shivam Bhasin Temasek Labs, Nanyang Technologival University, Signapore
  • Jan-Pieter D’Anvers imec-COSIC KU Leuven, Kasteelpark Arenberg 10 - bus 2452, 3001 Leuven, Belgium
  • Daniel Heinz Research Institute CODE, Universität der Bundeswehr München, Germany; Infineon Technologies, Am Campeon 1-15, 85579 Neubiberg, Germany
  • Thomas Pöppelmann Infineon Technologies, Am Campeon 1-15, 85579 Neubiberg, Germany
  • Michiel Van Beirendonck imec-COSIC KU Leuven, Kasteelpark Arenberg 10 - bus 2452, 3001 Leuven, Belgium

DOI:

https://doi.org/10.46586/tches.v2021.i3.334-359

Keywords:

Lattice-Based Cryptography, Side-Channel Attack, Fujisaki-Okamoto transform

Abstract

In this work, we are concerned with the hardening of post-quantum key encapsulation mechanisms (KEM) against side-channel attacks, with a focus on the comparison operation required for the Fujisaki-Okamoto (FO) transform. We identify critical vulnerabilities in two proposals for masked comparison and successfully attack the masked comparison algorithms from TCHES 2018 and TCHES 2020. To do so, we use first-order side-channel attacks and show that the advertised security properties do not hold. Additionally, we break the higher-order secured masked comparison from TCHES 2020 using a collision attack, which does not require side-channel information. To enable implementers to spot such flaws in the implementation or underlying algorithms, we propose a framework that is designed to test the re-encryption step of the FO transform for information leakage. Our framework relies on a specifically parametrized t-test and would have identified the previously mentioned flaws in the masked comparison. Our framework can be used to test both the comparison itself and the full decapsulation implementation.

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Published

2021-07-09

Issue

Section

Articles

How to Cite

Attacking and Defending Masked Polynomial Comparison for Lattice-Based Cryptography. (2021). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2021(3), 334-359. https://doi.org/10.46586/tches.v2021.i3.334-359