Optimizing BIKE for the Intel Haswell and ARM Cortex-M4

Authors

  • Ming-Shing Chen Ruhr University Bochum, Bochum, Germany
  • Tung Chou Academia Sinica, Taipei, Taiwan
  • Markus Krausz Ruhr University Bochum, Bochum, Germany

DOI:

https://doi.org/10.46586/tches.v2021.i3.97-124

Keywords:

constant-time implementations, NIST PQC standardization, Cortex-M4

Abstract

BIKE is a key encapsulation mechanism that entered the third round of the NIST post-quantum cryptography standardization process. This paper presents two constant-time implementations for BIKE, one tailored for the Intel Haswell and one tailored for the ARM Cortex-M4. Our Haswell implementation is much faster than the avx2 implementation written by the BIKE team: for bikel1, the level-1 parameter set, we achieve a 1.39x speedup for decapsulation (which is the slowest operation) and a 1.33x speedup for the sum of all operations. For bikel3, the level-3 parameter set, we achieve a 1.5x speedup for decapsulation and a 1.46x speedup for the sum of all operations. Our M4 implementation is more than two times faster than the non-constant-time implementation portable written by the BIKE team. The speedups are achieved by both algorithm-level and instruction-level optimizations.

Published

2021-07-09

Issue

Section

Articles

How to Cite

Optimizing BIKE for the Intel Haswell and ARM Cortex-M4. (2021). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2021(3), 97-124. https://doi.org/10.46586/tches.v2021.i3.97-124