Speed Reading in the Dark: Accelerating Functional Encryption for Quadratic Functions with Reprogrammable Hardware
Keywords:Functional encryption, Hardware implementation, Privacy enhancing technologies, HW/SW codesign, FPGA, System-on-chip, Machine learning
Functional encryption is a new paradigm for encryption where decryption does not give the entire plaintext but only some function of it. Functional encryption has great potential in privacy-enhancing technologies but suffers from excessive computational overheads. We introduce the first hardware accelerator that supports functional encryption for quadratic functions. Our accelerator is implemented on a reprogrammable system-on-chip following the hardware/software codesign methogology. We benchmark our implementation for two privacy-preserving machine learning applications: (1) classification of handwritten digits from the MNIST database and (2) classification of clothes images from the Fashion MNIST database. In both cases, classification is performed with encrypted images. We show that our implementation offers speedups of over 200 times compared to a published software implementation and permits applications which are unfeasible with software-only solutions.
How to Cite
Copyright (c) 2021 Milad Bahadori, Kimmo Järvinen, Tilen Marc, Miha Stopar
This work is licensed under a Creative Commons Attribution 4.0 International License.