DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering

  • Nils Albartus Ruhr University Bochum, Horst Görtz Institute for IT Security, Germany; Max Planck Institute for Security and Privacy, Bochum, Germany
  • Max Hoffmann Ruhr University Bochum, Horst Görtz Institute for IT Security, Germany; Max Planck Institute for Security and Privacy, Bochum, Germany
  • Sebastian Temme Ruhr University Bochum, Horst Görtz Institute for IT Security, Germany
  • Leonid Azriel Technion - Israel Institute of Technology, Haifa, Israel
  • Christof Paar Max Planck Institute for Security and Privacy, Bochum, Germany
Keywords: Hardware Reverse Engineering, Gate Level Netlists, Dataflow Analysis

Abstract

Reverse engineering of integrated circuits, i.e., understanding the internals of Integrated Circuits (ICs), is required for many benign and malicious applications. Examples of the former are detection of patent infringements, hardware Trojans or Intellectual Property (IP)-theft, as well as interface recovery and defect analysis, while malicious applications include IP-theft and finding insertion points for hardware Trojans. However, regardless of the application, the reverse engineer initially starts with a large unstructured netlist, forming an incomprehensible sea of gates.
This work presents DANA, a generic, technology-agnostic, and fully automated dataflow analysis methodology for flattened gate-level netlists. By analyzing the flow of data between individual Flip Flops (FFs), DANA recovers high-level registers. The key idea behind DANA is to combine independent metrics based on structural and control information with a powerful automated architecture. Notably, DANA works without any thresholds, scenario-dependent parameters, or other “magic” values that the user must choose. We evaluate DANA on nine modern hardware designs, ranging from cryptographic co-processors, over CPUs, to the OpenTitan, a stateof- the-art System-on-Chip (SoC), which is maintained by the lowRISC initiative with supporting industry partners like Google and Western Digital. Our results demonstrate almost perfect recovery of registers for all case studies, regardless whether they were synthesized as FPGA or ASIC netlists. Furthermore, we explore two applications for dataflow analysis: we show that the raw output of DANA often already allows to identify crucial components and high-level architecture features and also demonstrate its applicability for detecting simple hardware Trojans.
Hence, DANA can be applied universally as the first step when investigating unknown netlists and provides major guidance for human analysts by structuring and condensing the otherwise incomprehensible sea of gates. Our implementation of DANA and all synthesized netlists are available as open source on GitHub.

Published
2020-08-26
How to Cite
Albartus, N., Hoffmann, M., Temme, S., Azriel, L., & Paar, C. (2020). DANA Universal Dataflow Analysis for Gate-Level Netlist Reverse Engineering. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020(4), 309-336. https://doi.org/10.13154/tches.v2020.i4.309-336
Section
Articles