Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging

  • Bicky Shakya ECE Department, University of Florida
  • Haoting Shen ECE Department, University of Florida
  • Mark Tehranipoor ECE Department, University of Florida
  • Domenic Forte ECE Department, University of Florida
Keywords: IP Protection, Camouflaging, Reverse Engineering, SEM Imaging, ATPG, SAT

Abstract

Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. Existing methods of camouflaging are based on standard cells that can assume one of many Boolean functions, either through variation of transistor threshold voltage or contact configurations. Unfortunately, such methods lead to high area, delay and power overheads, and are vulnerable to invasive as well as non-invasive attacks based on Boolean satisfiability/VLSI testing. In this paper, we propose, fabricate, and demonstrate a new cell camouflaging strategy, termed as ‘covert gate’ that leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. We perform a comprehensive security analysis of covert gate, and show that it achieves high resiliency against SAT and test-based attacks at very low overheads. We also derive models to characterize the covert cells, and develop measures to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Published
2019-05-09
How to Cite
Shakya, B., Shen, H., Tehranipoor, M., & Forte, D. (2019). Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2019(3), 86-118. https://doi.org/10.13154/tches.v2019.i3.86-118
Section
Articles