AETHER: An Ultra-High Throughput and Low Energy Authenticated Encryption Scheme

Authors

  • Subhadeep Banik University of Lugano, Lugano, Switzerland
  • Andrea Caforio lowRISC C.I.C., Cambridge, United Kingdom
  • Tatsuya Ishikawa University of Hyogo, Kobe, Japan
  • Takanori Isobe University of Hyogo, Kobe, Japan
  • Mostafizar Rahman University of Hyogo, Kobe, Japan
  • Kosei Sakamoto Mitsubishi Electric Corporation, Kamakura, Japan; University of Hyogo, Kobe, Japan

DOI:

https://doi.org/10.46586/tches.v2025.i2.705-742

Keywords:

Authenticated encryption, Low energy, High throughput, AEGIS-like construction

Abstract

In this paper, we introduce AETHER, an authenticated encryption scheme that achieves ultra-high throughput and low energy consumption, supporting a 256- bit key and a 128-bit tag. While inspired by an AEGIS-like structure, AETHER stands out with a completely redesigned round-update function. We replace the AES round function with a new inner function optimized for ultra-low latency and energy consumption. This function incorporates Orthros’s S-box and a 16x16 binary matrix from Akleylek et al., leading to a 1.56 times reduction in energy consumption and a 1.25 times reduction in delay compared to the AES round function. To further optimize hardware performance, we design the general construction of the roundupdate function to be more hardware-friendly, allowing parallel execution of the inner function on all 128-bit words, thereby enhancing both throughput and security against collision-based forgery attacks. AETHER achieves a throughput of 2.1 Tbit/s and an energy consumption of only 204.31 nJ, in the Nangate 15 nm standard cell library and a throughput of 5.23 Tbit/s and energy consumption of 1.83 nJ using the CNFET-OCL 5nm library, outperforming all existing AEADs.

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Published

2025-03-04

Issue

Section

Articles

How to Cite

Banik, S., Caforio, A., Ishikawa, T., Isobe, T., Rahman, M., & Sakamoto, K. (2025). AETHER: An Ultra-High Throughput and Low Energy Authenticated Encryption Scheme. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(2), 705-742. https://doi.org/10.46586/tches.v2025.i2.705-742