TFHE Gets Real: an Efficient and Flexible Homomorphic Floating-Point Arithmetic

Authors

  • Loris Bergerat Zama, Paris, France; Université Caen Normandie, ENSICAEN, CNRS, Normandie Univ, GREYC UMR 6072, F-14000 Caen, France
  • Ilaria Chillotti
  • Damien Ligier
  • Jean-Baptiste Orfila Zama, Paris, France
  • Samuel Tap Zama, Paris, France

DOI:

https://doi.org/10.46586/tches.v2025.i2.126-162

Keywords:

Homomorphic Encryption, TFHE, Floating-Point

Abstract

Floating-point arithmetic plays a central role in computer science and is used in various domains where precision and computational scale are essential. One notable application is in machine learning, where Fully Homomorphic Encryption (FHE) can play a crucial role in safeguarding user privacy. In this paper, we focus on TFHE and develop novel homomorphic operators designed to enable the construction of precise and adaptable homomorphic floating-point operations. Integrating floating-point arithmetic within the context of FHE is particularly challenging due to constraints such as small message space and the lack of information during computation. Despite these challenges, we were able to determine parameters for common precisions (e.g., 32-bit, 64-bit) and achieve remarkable computational speeds, with 32-bit floating-point additions completing in 2.5 seconds and multiplications in approximately 1 second in a multi-threaded environment. These metrics provide empirical evidence of the efficiency and practicality of our proposed methods, which significantly outperform previous efforts. Our results demonstrate a significant advancement in the practical application of FHE, making it more viable for real-world scenarios and bridging the gap between theoretical encryption techniques and practical usability.

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Published

2025-03-04

Issue

Section

Articles

How to Cite

Bergerat, L., Chillotti, I., Ligier, D., Orfila, J.-B., & Tap, S. (2025). TFHE Gets Real: an Efficient and Flexible Homomorphic Floating-Point Arithmetic. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(2), 126-162. https://doi.org/10.46586/tches.v2025.i2.126-162