# Compact Circuits for Efficient Möbius Transform

## DOI:

https://doi.org/10.46586/tches.v2024.i2.481-521## Keywords:

Boolean Functions, Möbius transform, Solution of Equation System## Abstract

The Möbius transform is a linear circuit used to compute the evaluations of a Boolean function over all points on its input domain. The operation is very useful in finding the solution of a system of polynomial equations over *GF*(2) for obvious reasons. However the operation, although linear, needs exponential number of logic operations (around *n* · 2^{n−1} bit xors) for an *n*-variable Boolean function. As such, the only known hardware circuit to efficiently compute the Möbius Transform requires silicon area that is exponential in *n*. For Boolean functions whose algebraic degree is bound by some parameter *d*, recursive definitions of the Möbius Transform exist that requires only *O*(*n ^{d}*

^{+1}) space in software. However converting the mathematical definition of this space-efficient algorithm into a hardware architecture is a non-trivial task, primarily because the recursion calls notionally lead to a depth-first search in a transition graph that requires context switches at each recursion call for which straightforward mapping to hardware is difficult. In this paper we look to overcome these very challenges in an engineering sense. We propose a space efficient sequential hardware circuit for the Möbius Transform that requires only polynomial circuit area (i.e.

*O*(

*n*

^{d}^{+1})) provided the algebraic degree of the Boolean function is limited to

*d*. We show how this circuit can be used as a component to efficiently solve polynomial equations of degree at most

*d*by using fast exhaustive search. We propose three different circuit architectures for this, each of which uses the Möbius Transform circuit as a core component. We show that asymptotically, all the solutions of a system of

*m*polynomials in

*n*unknowns and algebraic degree

*d*over

*GF*(2) can be found using a circuit of silicon area proportional to

*m*·

*n*

^{d}^{+1}and circuit depth proportional to 2 · log

_{2}(

*n*−

*d*).

In the second part of the paper we introduce a fourth hardware solver that additionally aims to achieve energy efficiency. The main idea is to reduce the solution space to a small enough value by parallel application of Möbius Transform circuits over the first few equations of the system. This is done so that one can check individually whether the vectors of this reduced solution space satisfy each of the remaining equations of the system using lower power consumption. The new circuit has area also bound by

*m*·

*n*

^{d}^{+1}and has circuit depth proportional to d · log

_{2}

*n*. We also show that further optimizations with respect to energy consumption may be obtained by using depth-bound Möbius circuits that exponentially decrease run time at the cost of additional logic area and depth.

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## License

Copyright (c) 2024 Subhadeep Banik, Francesco Regazzoni

This work is licensed under a Creative Commons Attribution 4.0 International License.

## How to Cite

*IACR Transactions on Cryptographic Hardware and Embedded Systems*,

*2024*(2), 481-521. https://doi.org/10.46586/tches.v2024.i2.481-521