Masking Floating-Point Number Multiplication and Addition of Falcon

First- and Higher-order Implementations and Evaluations


  • Keng-Yu Chen National Taiwan University, Taipei, Taiwan
  • Jiun-Peng Chen National Taiwan University, Taipei, Taiwan; Academia Sinica, Taipei, Taiwan



Falcon, Floating-Point Arithmetic, Masking, Post-Quantum Cryptography, Side-Channel Analysis


In this paper, we provide the first masking scheme for floating-point number multiplication and addition to defend against recent side-channel attacks on Falcon’s pre-image vector computation. Our approach involves a masked nonzero check gadget that securely identifies whether a shared value is zero. This gadget can be utilized for various computations such as rounding the mantissa, computing the sticky bit, checking the equality of two values, and normalizing a number. To support the masked floating-point number addition, we also developed a masked shift and a masked normalization gadget. Our masking design provides both first- and higherorder mask protection, and we demonstrate the theoretical security by proving the (Strong)-Non-Interference properties in the probing model. To evaluate the performance of our approach, we implemented unmasked, first-order, and second-order algorithms on an Arm Cortex-M4 processor, providing cycle counts and the number of random bytes used. We also report the time for one complete signing process with our countermeasure on an Intel-Core CPU. In addition, we assessed the practical security of our approach by conducting the test vector leakage assessment (TVLA) to validate the effectiveness of our protection. Specifically, our TVLA experiment results for second-order masking passed the test in 100,000 measured traces.







How to Cite

Masking Floating-Point Number Multiplication and Addition of Falcon: First- and Higher-order Implementations and Evaluations. (2024). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024(2), 276-303.