Gadget-based Masking of Streamlined NTRU Prime Decapsulation in Hardware

Authors

  • Georg Land Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany
  • Adrian Marotzke Hamburg University of Technology, Hamburg, Germany; NXP Semiconductors, Hamburg, Germany
  • Jan Richter-Brockmann Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany
  • Tim Güneysu Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany; DFKI GmbH, Cyber-Physical Systems, Bremen, Germany

DOI:

https://doi.org/10.46586/tches.v2024.i1.1-26

Keywords:

PQC, Masking, FPGA, ASIC, Streamlined NTRU Prime, Higher-order Masking, Gadget-based Masking

Abstract

Streamlined NTRU Prime is a lattice-based Key Encapsulation Mechanism (KEM) that is, together with X25519, the default algorithm in OpenSSH 9. Based on lattice assumptions, it is assumed to be secure also against attackers with access to< large-scale quantum computers. While Post-Quantum Cryptography (PQC) schemes have been subject to extensive research in recent years, challenges remain with respect to protection mechanisms against attackers that have additional side-channel information, such as the power consumption of a device processing secret data. As a countermeasure to such attacks, masking has been shown to be a promising and effective approach. For public-key schemes, including any recent PQC schemes, usually, a mixture of Boolean and arithmetic techniques is applied on an algorithmic level. Our generic hardware implementation of Streamlined NTRU Prime decapsulation, however, follows an idea that until now was assumed to be solely applicable efficiently to symmetric cryptography: gadget-based masking. The hardware design is transformed into a secure implementation by replacing each gate with a composable secure gadget that operates on uniform random shares of secret values. In our work, we show the feasibility of applying this approach also to PQC schemes and present the first Public-Key Cryptography (PKC) – pre- and post-quantum – implementation masked with the gadget-based approach considering several trade-offs and design choices. By the nature of gadget-based masking, the implementation can be instantiated at arbitrary masking order. We synthesize our implementation both for Artix-7 Field-Programmable Gate Arrays (FPGAs) and 45nm Application-Specific Integrated Circuits (ASICs), yielding practically feasible results regarding the area, randomness requirement, and latency. We verify the side-channel security of our implementation using formal verification on the one hand, and practically using Test Vector Leakage Assessment (TVLA) on the other. Finally, we also analyze the applicability of our concept to Kyber and Dilithium, which will be standardized by the National Institute of Standards and Technology (NIST).

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Published

2023-12-04

How to Cite

Land, G., Marotzke, A., Richter-Brockmann, J., & Güneysu, T. (2023). Gadget-based Masking of Streamlined NTRU Prime Decapsulation in Hardware. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024(1), 1–26. https://doi.org/10.46586/tches.v2024.i1.1-26

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Articles