Provable Secure Parallel Gadgets


  • Francesco Berti Bar-Ilan University, Ramat-Gan 529002, Israel
  • Sebastian Faust Department of Computer Science, TU Darmstadt, Darmstadt, Germany
  • Maximilian Orlt Department of Computer Science, TU Darmstadt, Darmstadt, Germany



Random Probing Model, Masking, Composability, Leakage Diagram


Side-channel attacks are a fundamental threat to the security of cryptographic implementations. One of the most prominent countermeasures against side-channel attacks is masking, where each intermediate value of the computation is secret shared, thereby concealing the computation’s sensitive information. An important security model to study the security of masking schemes is the random probing model, in which the adversary obtains each intermediate value of the computation with some probability p. To construct secure masking schemes, an important building block is the refreshing gadget, which updates the randomness of the secret shared intermediate values. Recently, Dziembowski, Faust, and Zebrowski (ASIACRYPT’19) analyzed the security of a simple refreshing gadget by using a new technique called the leakage diagram. In this work, we follow the approach of Dziembowski et al. and significantly improve its methodology. Concretely, we refine the notion of a leakage diagram via so-called dependency graphs, and show how to use this technique for arbitrary complex circuits via composition results and approximation techniques. To illustrate the power of our new techniques, as a case study, we designed provably secure parallel gadgets for the random probing model, and adapted the ISW multiplication such that all gadgets can be parallelized. Finally, we evaluate concrete security levels, and show how our new methodology can further improve the concrete security level of masking schemes. This results in a compiler provable secure up to a noise level of O(1) for affine circuits and O(1/√n) in general.




How to Cite

Berti, F., Faust, S., & Orlt, M. (2023). Provable Secure Parallel Gadgets. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2023(4), 420–459.