Vectorized and Parallel Computation of Large Smooth-Degree Isogenies using Precedence-Constrained Scheduling


  • Kittiphon Phalakarn University of Waterloo, Waterloo, Canada
  • Vorapong Suppakitpaisarn The University of Tokyo, Tokyo, Japan
  • Francisco Rodríguez-Henríquez CINVESTAV-IPN, Mexico City, Mexico; Technology Innovation Institute, Abu Dhabi, UAE
  • M. Anwar Hasan University of Waterloo, Waterloo, Canada



Isogeny-based cryptography, Isogeny computation, Software optimization, Vectorization, Parallel computing, Precedence-constrained scheduling


Strategies and their evaluations play important roles in speeding up the computation of large smooth-degree isogenies. The concept of optimal strategies for such computation was introduced by De Feo et al., and virtually all implementations of isogeny-based protocols have adopted this approach, which is provably optimal for single-core platforms. In spite of its inherent sequential nature, several recent works have studied ways of speeding up this isogeny computation by exploiting the rich parallelism available in vectorized and multi-core platforms. One obstacle to taking full advantage of this parallelism, however, is that De Feo et al.’s strategies are not necessarily optimal in multi-core environments. To illustrate how the speed of vectorized and parallel isogeny computation can be improved at the strategylevel, we present two novel software implementations that utilize a state-of-the-art evaluation technique, called precedence-constrained scheduling (PCS), presented by Phalakarn et al., with our proposed strategies crafted for these environments. Our first implementation relies only on the parallelism provided by multi-core processors. The second implementation targets multi-core processors supporting the latest generation of the Intel’s Advanced Vector eXtensions (AVX) technology, commonly known as AVX-512IFMA instructions. To better handle the computational concurrency associated with PCS, we equip both implementations with extensive synchronization techniques. Our first implementation outperforms the implementation of Cervantes-Vázquez et al. by yielding up to 14.36% reduction in the execution time, when targeting platforms with two- to four-core processors. Our second implementation, equipped with four cores, achieves up to 34.05% reduction in the execution time compared to the single-core implementation of Cheng et al. of CHES 2022.







How to Cite

Vectorized and Parallel Computation of Large Smooth-Degree Isogenies using Precedence-Constrained Scheduling. (2023). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2023(3), 246-269.