“The SPEEDY Family of Block Ciphers: Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures”. IACR Transactions on Cryptographic Hardware and Embedded Systems 2021, no. 4 (August 11, 2021): 510–545. Accessed November 23, 2024. https://tches.iacr.org/index.php/TCHES/article/view/9074.