LEANDER, G.; MOOS, T.; MORADI, A.; RASOOLZADEH, S. The SPEEDY Family of Block Ciphers: Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2021, n. 4, p. 510–545, 2021. DOI: 10.46586/tches.v2021.i4.510-545. Disponível em: https://tches.iacr.org/index.php/TCHES/article/view/9074. Acesso em: 6 oct. 2022.