Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2024, n. 2, p. 403–425, 2024. DOI: 10.46586/tches.v2024.i2.403-425. Disponível em: https://tches.iacr.org/index.php/TCHES/article/view/11434.. Acesso em: 27 jul. 2024.