Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2020, n. 3, p. 269–306, 2020. DOI: 10.13154/tches.v2020.i3.269-306. Disponível em: https://tches.iacr.org/index.php/TCHES/article/view/8591.. Acesso em: 21 nov. 2024.