[1]
Bellizia, D. et al. 2021. Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype. IACR Transactions on Cryptographic Hardware and Embedded Systems. 2021, 3 (Jul. 2021), 390–417. DOI:https://doi.org/10.46586/tches.v2021.i3.390-417.