[1]
Fallnich, D. et al. 2024. Efficient ASIC Architecture for Low Latency Classic McEliece Decoding. IACR Transactions on Cryptographic Hardware and Embedded Systems. 2024, 2 (Mar. 2024), 403–425. DOI:https://doi.org/10.46586/tches.v2024.i2.403-425.