TY - JOUR AU - Wang, Wen AU - Tian, Shanquan AU - Jungk, Bernhard AU - Bindel, Nina AU - Longa, Patrick AU - Szefer, Jakub PY - 2020/06/19 Y2 - 2024/03/28 TI - Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA JF - IACR Transactions on Cryptographic Hardware and Embedded Systems JA - TCHES VL - 2020 IS - 3 SE - Articles DO - 10.13154/tches.v2020.i3.269-306 UR - https://tches.iacr.org/index.php/TCHES/article/view/8591 SP - 269-306 AB - <p>This paper presents a set of efficient and parameterized hardware accelerators that target post-quantum lattice-based cryptographic schemes, including a versatile cSHAKE core, a binary-search CDT-based Gaussian sampler, and a pipelined NTT-based polynomial multiplier, among others. Unlike much of prior work, the accelerators are fully open-sourced, are designed to be constant-time, and can be parameterized at compile-time to support different parameters without the need for re-writing the hardware implementation. These flexible, publicly-available accelerators are leveraged to demonstrate the first hardware-software co-design using RISC-V of the post-quantum lattice-based signature scheme qTESLA with provably secure parameters. In particular, this work demonstrates that the NIST’s Round 2 level 1 and level 3 qTESLA variants achieve over a 40-100x speedup for key generation, about a 10x speedup for signing, and about a 16x speedup for verification, compared to the baseline RISC-V software-only implementation. For instance, this corresponds to execution in 7.7, 34.4, and 7.8 milliseconds for key generation, signing, and verification, respectively, for qTESLA’s level 1 parameter set on an Artix-7 FPGA, demonstrating the feasibility of the scheme for embedded applications.</p> ER -