@article{Belkheyar_Daemen_Dobraunig_Ghosh_Rasoolzadeh_2022, title={BipBip: A Low-Latency Tweakable Block Cipher with Small Dimensions}, volume={2023}, url={https://tches.iacr.org/index.php/TCHES/article/view/9955}, DOI={10.46586/tches.v2023.i1.326-368}, abstractNote={<p>Recently, a memory safety concept called Cryptographic Capability Computing (C<sup>3</sup>) has been proposed. C<sup>3</sup> is the first memory safety mechanism that works without requiring extra storage for metadata and hence, has the potential to significantly enhance the security of modern IT-systems at a rather low cost. To achieve this, C<sup>3</sup> heavily relies on ultra-low-latency cryptographic primitives. However, the most crucial primitive required by C<sup>3</sup> demands uncommon dimensions. To partially encrypt 64-bit pointers, a 24-bit tweakable block cipher with a 40-bit tweak is needed. The research on low-latency tweakable block ciphers with such small dimensions is not very mature. Therefore, designing such a cipher provides a great research challenge, which we take on with this paper. As a result, we present BipBip, a 24-bit tweakable block cipher with a 40-bit tweak that allows for ASIC implementations with a latency of 3 cycles at a 4.5 GHz clock frequency on a modern 10 nm CMOS technology.</p>}, number={1}, journal={IACR Transactions on Cryptographic Hardware and Embedded Systems}, author={Belkheyar, Yanis and Daemen, Joan and Dobraunig, Christoph and Ghosh, Santosh and Rasoolzadeh, Shahram}, year={2022}, month={Nov.}, pages={326–368} }