@article{Fritzmann_Van Beirendonck_Basu Roy_Karl_Schamberger_Verbauwhede_Sigl_2021, title={Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography}, volume={2022}, url={https://tches.iacr.org/index.php/TCHES/article/view/9303}, DOI={10.46586/tches.v2022.i1.414-460}, abstractNote={<p>Side-channel attacks can break mathematically secure cryptographic systems leading to a major concern in applied cryptography. While the cryptanalysis and security evaluation of Post-Quantum Cryptography (PQC) have already received an increasing research effort, a cost analysis of efficient side-channel countermeasures is still lacking. In this work, we propose a masked HW/SW codesign of the NIST PQC finalists Kyber and Saber, suitable for their different characteristics. Among others, we present a novel masked ciphertext compression algorithm for non-power-of-two moduli. To accelerate linear performance bottlenecks, we developed a generic Number Theoretic Transform (NTT) multiplier, which, in contrast to previously published accelerators, is also efficient and suitable for schemes not based on NTT. For the critical non-linear operations, masked HW accelerators were developed, allowing a secure execution using RISC-V instruction set extensions. With the proposed design, we achieved a cycle count of K:214k/E:298k/D:313k for Kyber and K:233k/E:312k/D:351k for Saber with NIST Level III parameter sets. For the same parameter sets, the masking overhead for the first-order secure decapsulation operation including randomness generation is a factor of 4.48 for Kyber (D:1403k)<br>and 2.60 for Saber (D:915k).</p>}, number={1}, journal={IACR Transactions on Cryptographic Hardware and Embedded Systems}, author={Fritzmann, Tim and Van Beirendonck, Michiel and Basu Roy, Debapriya and Karl, Patrick and Schamberger, Thomas and Verbauwhede, Ingrid and Sigl, Georg}, year={2021}, month={Nov.}, pages={414–460} }